1. Field of the Invention
The present invention relates to bi-directional ESD diode structures and, more particularly, to a bi-directional ESD diode structure with ultra-low capacitance that consumes a small amount of silicon real estate.
2. Description of the Related Art
An electrostatic discharge (ESD) circuit is a circuit that protects an integrated circuit from voltage spikes, which commonly occur when the integrated circuit is handled. In operation, an ESD circuit provides an open circuit between a first node and a second node when the voltage difference across the first and second nodes is less than a breakdown voltage.
However, when the voltage difference across the first and second nodes spikes up to be equal to or greater than the breakdown voltage, the ESD circuit provides a low-resistance current path between the first and second nodes. A bi-directional ESD circuit provides protection regardless of whether the voltage on the first node rises with respect to the second node, or the voltage on the second node rises with respect to the first node.
Conventional bi-directional ESD circuits typically include a combination of Zener diodes and high-breakdown-voltage avalanche diodes. One of the drawbacks to utilizing a conventional combination of Zener and avalanche diodes is that the metal lead, which is required to connect the Zener and avalanche diodes together, consumes a large amount of silicon real estate.
FIG. 1 shows a cross-sectional view that illustrates an example of a prior-art bi-directional ESD diode structure 100. As shown in FIG. 1, diode structure 100 includes a p+ substrate region 110, an n+ epitaxial region 112 that touches the top surface of p+ substrate region 110, and a p+ region 114 that touches the top surface of n+ epitaxial region 112.
Diode structure 100 also includes a trench isolation structure 116 that laterally surrounds a portion of p+ substrate region 110, n+ epitaxial region 112, and p+ region 114. Diode structure 100 further includes a non-conductive layer 120 that touches and lies over p+ region 114, and a metal contact 122 that touches and extends through non-conductive layer 120 to make an electrical connection to p+ region 114. In addition, diode structure 100 includes a non-conductive layer 124 that touches and lies over non-conductive layer 120 and metal contact 122. Further, non-conductive layer 124 has an opening 130 that exposes metal contact 122.
In operation, p+ region 114 forms the anode and n+ epitaxial region 112 forms the cathode of a top Zener diode, while p+ substrate region 110 forms the anode and n+ epitaxial region 112 forms the cathode of a bottom Zener diode, where the cathodes of the two diodes are connected together.
Thus, when the voltage on metal contact 122 spikes up with respect to the voltage on p+ substrate region 110 and exceeds the breakdown voltage of the bottom Zener diode, a discharge current flows from metal contact 122 to p+ substrate region 110. On the other hand, when the voltage on p+ substrate region 110 spikes up with respect to the voltage on metal contact 122 and exceeds the breakdown voltage of the top Zener diode, a discharge current flows from p+ substrate region 110 to metal contact 122.
One of the advantages of diode structure 100 is that diode structure 100 consumes much less silicon real estate than a conventional combination of Zener and avalanche diodes. However, one of the disadvantages of diode structure 100 is that diode structure 100 has a much higher capacitance than a conventional combination of Zener and avalanche diodes.
For example, the dopant concentrations of substrate region 110, n+ epitaxial region 112, and p+ region 114 can be selected so that diode structure 100 has a capacitance of 14.7 pF, the top Zener diode has a breakdown voltage of −6.5V, and the bottom Zener diode has a breakdown voltage of +11V. Diode structures with a higher capacitance, however, cannot be used with high-speed signal applications, such as USB 3.0 and HDMI 1.4. Thus, there is a need for a bi-directional ESD diode structure with a low capacitance that also consumes a small amount of silicon real estate.